else if (( DEPTH == 4096) & (DATA_W == 32)) begin: gen_sram_2048w_32b_4096_32
  logic [10:0] addr_temp;
  logic [31:0] wdata_temp;
  logic [31:0] bweb ;
  logic [1:0][31:0] rdata_temp  ;
  logic [1:0] web;
  logic [1:0] ceb;
  logic        read_en;
  logic        addr_top_q;
    assign  addr_temp = addr[10:0];
    assign  wdata_temp = wdata[31:0];

   // current cycle has valid read operation
   assign read_en = cs & ~wr;
   always @(posedge clk)
    if (read_en) //if current cycle has valid read operation, flop address upper bits to select read data next cycle 
      addr_top_q <= addr[11];

   assign  bweb = {~wen[31:0]};

   assign  rdata = 
        (addr_top_q == 1'b1) ? rdata_temp[1] :
                               rdata_temp[0];


    for(genvar i=0; i<2; i++) begin

   
    assign  web[i] = ~(wr & (addr[11]==i[0]));  

    assign  ceb[i] = ~(cs & (addr[11]==i[0]));

     TEM5N28HPCPLVTA2048X32M8SWSO sram_0 
      (.SLP  (1'b0),
      .SD   (1'b0),
      .A    (addr_temp),
      .D    (wdata_temp),
      .BWEB (bweb),
      .Q    (rdata_temp[i]),
      .WEB  (web[i]),
      .CEB  (ceb[i]),
      .CLK  (clk)
    );
    end
  end  //gen_sram_2048w_32b_4096_32
